FPGA Specifications

[Flaming Zephyr]

I'm not really sure if this is the right section, but i just had a question. Most of you know the purpose of FPGA and Xboxes. Modchips. If you look at my thread in XBox Discussion, I wasnt to make my own modchip. So i just wanted to know if these FPGA specifications would be adequate enough for a ModChip (FPGA is the Field-Programmable Gate Array, it handles all the I/O stuff for the chip, and basically tells the chip what to do).

FPGA Specs:

High-density architecture with 4,608 to 68,416 LEs

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M4K embedded memory blocks

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Up to 1.1 Mbits of RAM available without reducing available
logic

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4,096 memory bits per block (4,608 bits per block including 512
parity bits)

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Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,
and ×36

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True dual-port (one read and one write, two reads, or two
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

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Byte enables for data input masking during writes

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Up to 260-MHz operation

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Embedded multipliers

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Up to 150 18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-MHz
performance

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Optional input and output registers

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Advanced I/O support

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High-speed differential I/O standard support, including LVDS,
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential
SSTL

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Single-ended I/O standard support, including 2.5-V and 1.8-V,
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI
and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,
and 1.8-V LVTTL

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Peripheral Component Interconnect Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V
operation at 33 or 66 MHz for 32- or 64-bit interfaces

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PCI Express with an external TI PHY and an Altera PCI Express
×1 Megacore® function

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133-MHz PCI-X 1.0 specification compatibility

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High-speed external memory support, including DDR, DDR2,
and SDR SDRAM, and QDRII SRAM supported by drop in
Altera IP MegaCore functions for ease of use

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Three dedicated registers per I/O element (IOE): one input
register, one output register, and one output-enable register

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Programmable bus-hold feature

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Programmable output drive strength feature

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Programmable delays from the pin to the IOE or logic array

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I/O bank grouping for unique VCCIO and/or VREF bank
settings

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MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and
3.3-interfaces

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Hot-socketing operation support

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Tri-state with weak pull-up on I/O pins before and during
configuration

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Programmable open-drain outputs

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Series on-chip termination support

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Flexible clock management circuitry

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Hierarchical clock network for up to 402.5-MHz performance

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Up to four PLLs per device provide clock multiplication and
division, phase shifting, programmable duty cycle, and external
clock outputs, allowing system-level clock management and
skew control

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Up to 16 global clock lines in the global clock network that drive
throughout the entire device

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Device configuration

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Fast serial configuration allows configuration times less than
100 ms

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Decompression feature allows for smaller programming file
storage and faster configuration times

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Supports multiple configuration modes: active serial, passive
serial, and JTAG-based configuration

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Supports configuration through low-cost serial configuration
devices

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Device configuration supports multiple voltages (either 3.3, 2.5,
or 1.8 V)

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Intellectual property

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Altera megafunction and Altera MegaCore function support,
and Altera Megafunctions Partners Program (AMPPSM)
megafunction support, for a wide range of embedded
processors, on-chip and off-chip interfaces, peripheral
functions, DSP functions, and communications functions and

● Nios II Embedded Processor support

What do you think?